1. Technical Field
The disclosure relates to hardware support for partitioning a system into multiple subsystems so each may provide a distinct operating system environment or partition within the system. The disclosure particularly relates to systems which utilize directly addressable memory subsystems both locally by a processor or group of processors (node) and remotely by the other nodes or processors in the same system.
2. Description of the Related Art
With the advent of multiprocessor computer systems which share memory across the system, many personal computers, work stations, and server computing machines using such multiple processor hardware architecture have become popular. Multiprocessor architecture has become an important feature because of the shared processing capabilities of coordinated multiprocessor systems which enhance performance by sharing memory across an entire system, all of which may be accessible by multiple groups of multiprocessors (nodes) combined in a single system. Multiple processor computers can include large numbers of individual processors arranged in separate groups, each of which are associated with particular memory systems but all of which are coordinated with crossbar switch architecture systems allowing for data, data tagging and address control across the entire system. In the usual system architectural arrangement, processing boards, each of which has at least one processor and associated main memory, are connected by a high-speed crossbar switch communicating with each group of processors so as to maintain cache coherency among the various processors across the system.
Users of a multiprocessor system have varying needs for the level of computing power available from that system, or wish to run different operating systems simultaneously on the system. It is desirable to have the capability of dividing such a system running a single operating system instance into multiple subsystems which each provides its own distinct operating system environment. By partitioning a multiprocessor system in such a fashion, the system could be reconfigured on demand to adjust the allocation of system resources across the operating system partitions to provide the appropriate sizing of resources to each partition. Various patents issued relating to the field of the present invention teach multiple processor systems which have memory resource management techniques. The disclosures considered below illustrate the background art against which the advantages of the present invention will become apparent and be fully appreciated.
U.S. Pat. No. 5,905,998 issued to Ebrahim, et al., defines a system in which system memory and multiple processor units are each distinct rather than in a system where memory and processors are grouped together into nodes, each containing multiple processors and memory and where the mobile nodes exist in the operation of the system. This disclosure also requires the use and definition of master and duplicate cache tags. U.S. Pat. No. 5,905,998 does not teach a method of partitioning of a processor system.
U.S. Pat. No. 6,088,770 issued to Tarui, et al., describes a multiprocessor system that is partitioned into various nodes which may allow different operating systems to function similar to the present invention. This disclosure utilizes all the system memory shared as one, a distinct disadvantage. Further, U.S. Pat. No. 6,088,770 does not teach coherent sharing of memory between partitions.
U.S. Pat. No. 6,035,378 issued to James teaches memory page access monitoring logic that may provide information about memory access patterns, but does not teach the subject of partitioning memory systems.
U.S. Pat. No. 6,075,938 issued to Bugnion, et al., defines the use of layers of software that are inserted between the operating system and the application software such as to allow multiple operating systems to run concurrently on the system through the use of a virtual machine monitor.
U.S. Pat. No. 5,926,829 issued to Hagersten, et al., teaches a method for selecting between two different caching modes between NUMA and COMA systems. The overall architecture disclosed in U.S. Pat. No. 5,926,829 employs distributed memory directories and interfaces and does not to teach partitioning as presently disclosed.
U.S. Pat. No. 5,893,144 issued to Wood, et al., is almost identical to the disclosure and teachings set forth in Hagersten, et al. above.
U.S. Pat. No. 5,887,138 issued to Hagersten, et al., is similar to the '829 and '144 patent issued to Hagersten and Wood above.
U.S. Pat. No. 6,049,853 issued to Kingsbury, et al., defines a method in which portions of system memory used to store program code are copied into other locations in memory so that two users of the system may both have the code as local to increase system performance. This patent does not teach partitioning system resources.
U.S. Pat. No. 3,641,505 describes an older method of partitioning a system by using a less sophisticated method of providing large crossbar systems which interconnect processor modules of a particular type to other modules of types that require communication paths. Controls of the crossbar in this disclosure allows or disallows communications between them, thus effecting a crude partitioning method.
U.S. Pat. No. 6,021,479 issued to Stevens defines a memory management system which effects memory management Policies within the system. This disclosure provides for optimization of memory access latencies on a single system utilizing one operating system at a time.